That's actually an almost reasonable definition of CISC for laypeople. Take a look at the definition on wikipedia.
A complex instruction set computer (CISC, play /ˈsɪsk/)
is a computer where single instructions can execute several
low-level operations (such as a load from memory, an arithmetic
operation, and a memory store) and/or are capable of multi-step
operations or addressing modes within single instructions.
Now the reality is that on the whole things are not quite as cut and dry. In this case they're doing it to give access to dedicated hardware for power gains most likely, which is why something that's typically close to RISC would add something like that. As time has gone on, both CISC and RISC systems have moved more toward a blend of both in-order to get the best of both worlds, from what i've heard interally most x86 chips actually work like a risc chip they just translate between things in the instruction decoder.
> A complex instruction set computer (CISC, play /ˈsɪsk/)
> is a computer where single instructions ... and/or are
> capable of multi-step operations ... within single
> instructions.
What's a "multi-step operation"?
I ask because I worked on the microarchitecture (read "implementation") of a microprocessor that had what was generally regarded as a very RISC instruction set.
Yet, almost every instruction had multiple steps. Yes, including integer add.
Were we doing something wrong?
And no, "one cycle fundamental operations" doesn't change things. Dividing things into cycles is a design choice. For example, one might reasonably do integer adds in two steps.
If those ops are register-register, how are they necessarily not-RISC?
Yes, division is inherently more complex than bitwise NAND, but it's not obvious to me where the line is that you find so clear.
FWIW, I've seen a very serious architecture proposal that used two instructions for memory-reads. (It had one instruction for memory writes.) Along those lines, register-value fetch can be moved into a separate instruction....
The sse1 instruction provide the option of register-register, but also support register-memory. I didn't realize it supported register-register mode, so now I see why it would be less obvious to you.
Why is copying a value from register to memory (or memory to register) "RISC" while performing some logical operation to the value to the value as moves "not risc"?
I'd agree that memory to memory is "not risc", but given the amount of work necessary to do a register access, it's unclear why doing work on a value is "not risc".
Datapaths are NOT the complex part of a microprocessor.
Mmm, I think RISC has to be a relative term. (It does, after all, have "reduced" in its name, which implies a comparison with a less-reduced alternative.) So every time processor A has an instruction that can only be done with a sequence of several instructions on processor B, that is evidence that B is more RISCy than A.
